Color image processing to convert an image into a renderable image, that is an image capable of being rendered, invariably involves some form of color and data transformation to convert the pixels of the color image having colorimetry defined in a first color space into a renderable image comprising a plurality of renderable pixels, that is a pixel capable of being rendered, defined by a device in a second color space of the rendering device. This color image processing may require high data rates, for example, data rates in the range of 100 Mpix/s to 2 Gpix/s. There exists many ways of achieving these data rates. One way is to utilise a high-end server with the rendering device and another is to implement the image processing pipeline in an Application Specific Integrated Circuit (ASIC) or a Field-Programmable Gate Array (FPGA). The former approach greatly increases the costs of the rendering device to the point of making them unviable. The latter approach, pipeline on an ASIC or FPGA, lacks flexibility. An ASIC's development process, for example, is slow, the algorithms to implement have to be decided well in advance, and frequently several different models of the rendering device have to share an ASIC in order to reach the volumes that make it cost-effective.